========================================================================
    Logic Analyser 1.3
========================================================================
by Vasantha Crabb <_merlin@operamail.com>
http://members.xoom.com/_merlin/


========================================================================
    INTRODUCTION
========================================================================
Welcome to Logic Analyser 1.3, the first piece of "virtual test
equipment" software for the Texas Instruments TI-8x graphing calculator
family.  Logic Analyser was the winner of the Electronics Australia Idea
of the Month prize for July 1999.

Logic Analyser lets you simultaneously capture digital waveforms on two
channels and graph them side-by-side.  It has five trigger modes and a
wide range of sample rates.

With no interface circuitry, Logic Analyser is compatible with 5 Volt
TTL and CMOS.  With a simple diode interface, it is compatible with 5V
TTL and 5V CMOS with any supply voltage greater than or equal to 5V.
Using level shifting circuitry, Logic Analyser can be used with any
logic family.

Logic Analyser is e-mail ware!  If you use it, send me a note.

The latest version of Logic Analyser will always be available from my
website at http://members.xoom.com/_merlin/.


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    DISTRIBUTION CONTENTS
========================================================================
The distribution of Logic Analyser should contain the following files:

LOGIC_O  82P    The OS-82 version program file.
LOGIC_C  82P    The CrASH version program file.
LOGIC_83 83P    The TI-83 version program file.
LOADER   83G    Support file for TI-83 users without SOS or AShell.
LOGIC    HTM    HTML documentation.
SAMPLE   GIF    Sample screenshot of Logic Analyser.
LOGIC    TXT    This file.
INTRFACE TXT    Text file describing interface circuits.
DIODES   GIF    Schematic for a simple diode interface circuit.
MOSFET   GIF    Schematic for a MOSFET interface circuit.
SOURCE   TXT    Source code documentation.
LOGIC_O  ASM    The source code for the OS-83 version.
LOGIC_C  ASM    The source code for the CrASH version.
LOGIC_83 ASM    The source code for the TI-83 version.
KEYCODES H      Header file used in OS-82 version.


========================================================================
    INSTALLATION
========================================================================
To download the software to your calculator, you will need some kind of
link hardware and software for your computer.  If you can solder and
identify components, and have an IBM PC-compatible computer, I recommend
building your own link cable.  See the ticalc.org website at
http://www.ticalc.org/ for more information.  Otherwise, you will have
to buy an expensive Texas Instruments GraphLink cable.

I recomend that you use some kind of interface circuit to protect both
your calculator and the circuits you'll be testing.  See INTRFACE.TXT
Circuits below for more information.

------------------------------------
OS-82 Version
------------------------------------
Logic Analyser requires a TI-82 calculator running OS-82.  The program
takes up 846 bytes of memory.  No additional memory is allocated while
running.  OS-82 1.1 is available from ticalc.org.

If you haven't already done so, install OS-82.  Download the file
"LOGIC_O.82P" to your calculator.  Logic Analyser can now be run like
any other OS-82 program.

Logic Analyser has been tested on TI-82s with ROM versions 18.0 and 19.0
using OS-82 1.1.  It is compatible with with most interrupt-patching
software.  Although I don't see any reasons why Logic Analyser shouldn't
be compatible with other ROM versions, if you do experience any
problems, please notify me.

------------------------------------
CrASH Version
------------------------------------
Logic Analyser requires a TI-82 calculator running CrASH.  The program
takes up 781 bytes of memory.  CrASH 1.6 is available from ticalc.org.

If you haven't already done so, install CrASH.  Download the file
"LOGIC_C.82P" to your calculator.  Logic Analyser can now be run like
any other CrASH program.

Logic Analyser has been tested on TI-82s with ROM versions 18.0 and 19.0
using CrASH 1.6.  It is compatible with with most interrupt-patching
software.  Although I don't see any reasons why Logic Analyser shouldn't
be compatible with other ROM versions, if you do experience any
problems, please notify me.

------------------------------------
TI-83 Version
------------------------------------
Logic Analyser for TI-83 will run under AShell, SOS or ZASMLOAD.  Logic
Analyser will not run under Aurora.  AShell 1.0 and SOS 2.0 are
available from ticalc.org.  ZASMLOAD is included with Logic Analyser.
The actual program variable takes up 772 bytes of memory.  You'll need
about 1 kB of free memory to run Logic Analyser.  I recommend using SOS,
as it has a much wider range of programs available for it, and will run
all AShell programs.

Download the file "LOGIC_83.83P" to your calculator.  If you don't have
AShell or SOS installed, download the file "LOADER.83G" to your
calculator.  If you get a Duplicate Name error, just choose Overwrite.

If you're using AShell, choose ZLOGIC from the program list to run Logic
Analyser.  If you're using SOS, choose Logic Analyser 1.3.  To run Logic
Analyser using ZASMLOAD, execute the command prgmLOGIC from the home
screen.

Logic Analyser has been tested on TI-83s with ROM versions 1.0600,
1.07000 and 1.10 using AShell 1.0, SOS 2.0 and ZASMLOAD.  Although I
don't see any reasons why Logic Analyser shouldn't be compatible with
other ROM versions, if you do experience any problems, please notify me.


========================================================================
    USING LOGIC ANALYSER
========================================================================
First run Logic Analyser.  You will then see the Logic Analyser screen
with the program title at the top, a status line, two lines displaying
the setting and two lines with the names of the channels and their
connections on the link port.

Now plug your interface circuit into the calculator's link port (or
SPiNTERFACE port if fitted) and connect the probes to the circuit under
test.  If you attach the interface circuit to the calculator before you
run Logic Analyser, your calculator may appear to hang.  This is normal,
simply unplug the interface and the calculator should return to normal
operation.  You should also disconnect the interface circuit before
exiting from Logic Analyser.

Select a trigger mode and sampling delay with the arrow keys.  The up
and down arrows switch between changing trigger mode and the sampling
delay.  The left and right arrow keys change the trigger mode or the
sampling delay.  Press the CLEAR key to exit from Logic Analyser.

The trigger modes are as follows:

Manual:             Triggers immediately.
Channel 1 Rising:   Triggers when the Channel 1 signal undergoes a low
                    to high transition.
Channel 1 Falling:  Triggers when the Channel 1 signal undergoes a high
                    to low transition.
Channel 2 Rising:   Triggers when the Channel 2 signal undergoes a low
                    to high transition.
Channel 2 Falling:  Triggers when the Channel 2 signal undergoes a high
                    to low transition.

The sampling delay setting corresponds to the number of DJNZ
instructions (rather like a FOR loop) executed between samples.  The
higher this number the lower the sample rate.  Values range from 000 to
255.  At 000, you can neatly capture a byte from an AT keyboard.  At
255, a byte on a 300bps serial bus takes up most of the screen.  The
nominal sample rate can be calculated as

6000000 / (48 + (13 x D))

where D is the sampling delay setting.  So with a setting of 000, the
sample rate is 125 kS/s, a setting of 004 gives 60 kS/s, a setting of
054 gives 8 kS/s, etc.  Note that the accuracy of the sample rate
depends on the accuracy of the 6MHz CPU clock, which may not be spot-on,
and may even vary with temperature.  Also, if you "overclock" your
calculator, this will affect the sample rate, too.  Logic Analyser's
sample rate is not affected by Turbo or Game Wizard.  These, and similar
pieces of software, affect the timing of some programs by increasing the
rate of the timer interrupts (acceleration) or installing very time-
consuming interrupt service routines (deceleration).  Logic Analyser
disables interrupts during triggering and acquisition, and is therefore
not affected by any interrupt-related software.

When you press ENTER, Logic Analyser goes into the "armed" state and
waits for a trigger event to occur.  When the trigger event occurs,
Logic Analyser takes 96 samples and graphs them on the screen.  Note
that, to minimise response time, Logic Analyser does not read the keypad
while it is waiting for a trigger event, so the program must be
triggered before you can exit.  This can be achieved by momentarily
shorting both channel inputs to ground.

Note that Logic Analyser, to avoid hanging when connected to a live
circuit, does not support APD, the Get( instruction from another
calculator or the TI-GraphLink Get LCD command.  As of version 1.3,
Logic Analyser does support sleep between keystrokes while idle.


========================================================================
    CREDITS
========================================================================
The port, RAM and ROM documentation provided with Ash 3.0 proved
invaluable while writing the TI-82 versions.  Texas Instruments' TI-83
documentation was the only reference I needed while doing the TI-83
port.  Randy Gluvna's TI8xEMU is great for initial testing.  I hardly ever
crach my calculators any more.  Thanks to Matt "Bush-Pig" Saulys for
lending me a his TI-82 (version 18.0) and to Paul Jashinski and Peter
Dunstan for letting me borrow their TI-83s.


========================================================================
    DISCLAIMER AND COPYRIGHT
========================================================================
Logic Analyser is provided "as is".  Although I have taken measures to
ensure its reliability and safety, I cannot guarantee that no problems
remain.  I accept no responsibility for any damage which Logic Analyser
may cause, directly or indirectly, to your calculator, your data or the
circuits you use it to test.

Logic Analyser is Copyright (c) 1999 Vasantha Crabb.  You may distribute
unmodified copies of the zip archive between computers, or unmodified
copies of the program between calculators.  You may use the source code
in your own projects, as long as it constitutes no more than fifty
percent of the total code and I am acknowledged in the credits.  You may
not distribute modified copies of the program, the documentation or the
source code without my express permission.  You may not use source code
from logic analyser in any commercial software.


========================================================================
    VERSION HISTORY
========================================================================
1.3 - 17 December 1999
    Smaller code size, lower power consumption.  Better TI-83 and CrASH
    support (fully native, no porting throwbacks).  More extensively
    tested.
1.2 - 10 August 1999
    CrASH and TI-83 versions released.  Improved triggering, narrower
    pulses now detected.  Fixed some documentation errors.
1.1 - 7 July 1999
    Minor update.  Smaller code size, faster sampling, determined
    nominal sample rates.
1.0 - 15 April 1999
    Initial release.  Two channels, five triggering modes, wide range of
    sample rates.
